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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. _______________general description the MAX3100 universal asynchronous receiver transmit- ter (uart) is the first uart specifically optimized for small microcontroller-based systems. using an spi/microwire interface for communication with the host microcontroller (c), the MAX3100 comes in a com- pact 16-pin qsop. the asynchronous i/o is suitable for use in rs-232, rs-485, ir, and opto-isolated data links. ir-link communication is easy with the MAX3100? infrared data association (irda) timing mode. the MAX3100 includes a crystal oscillator and a baud- rate generator with software-programmable divider ratios for all common baud rates from 300 baud to 230k baud. a software- or hardware-invoked shutdown lowers quies- cent current to 10?, while allowing the MAX3100 to detect receiver activity. an 8-word-deep first-in/first-out (fifo) buffer minimizes processor overhead. this device also includes a flexible interrupt with four maskable sources, including address recognition on 9-bit networks. two hardware-handshak- ing control lines are included (one input and one output). the MAX3100 is available in 14-pin plastic dip and small, 16-pin qsop packages in the commercial and extended temperature ranges. ________________________applications hand-held instruments intelligent instrumentation uart in spi systems small networks in hvac or building control isolated rs-232/rs-485: directly drives opto-couplers low-cost ir data links for computers/peripherals ____________________________features ? 16-pin qsop package (8-pin so footprint): smallest uart available ? full-featured uart: ?rda sir timing compatible ?-word fifo minimizes processor overhead at high data rates ?p to 230k baud with a 3.6864mhz crystal ?-bit address-recognition interrupt ?eceive activity interrupt in shutdown ? spi/microwire-compatible ? interface ? lowest power: ?50? operating current at 3.3v ?0? in shutdown with receive interrupt ? +2.7v to +5.5v supply voltage in operating mode ? schmitt-trigger inputs for opto-couplers ? tx and rts outputs sink 25ma for opto-couplers MAX3100 spi/microwire-compatible uart in qsop-16 ________________________________________________________________ maxim integrated products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc tx rx rts cs sclk dout din top view MAX3100 cts x1 x2 gnd shdn irq dip 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v cc tx rx rts n.c. cts x1 x2 din dout sclk cs n.c. irq shdn gnd MAX3100 qsop __________________________________________________________pin configurations 19-1259; rev 0; 7/97 part MAX3100cpd MAX3100cee 0? to +70? 0? to +70? temp. range pin-package 14 plastic dip 16 qsop ______________ordering information typical operating circuit appears at end of data sheet. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. MAX3100epd MAX3100eee -40? to +85? -40? to +85? 14 plastic dip 16 qsop
MAX3100 spi/micr owir e-compatible uar t in qsop-16 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +2.7v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are measured at 9600 baud at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ........................................................................... +6v input voltage to gnd ( cs , shdn , x1, cts , rx, din, sclk) .... -0.3v to (v cc + 0.3v) output voltage to gnd (dout, rts , tx, x2) .............................. -0.3v to (v cc + 0.3v) irq ........................................................................... -0.3v to 6v tx, rts output current .................................................... 100ma x2, dout, irq short-circuit duration (to v cc or gnd) ......................................................... indefinite continuous power dissipation (t a = +70 c) plastic dip (derate 10.00mw/ c above +70 c) .......... 800mw qsop (derate 8.30mw/ c above +70 c) ..................... 667mw operating temperature ranges MAX3100c_ _ ...................................................... 0 c to +70 c MAX3100e_ _ ................................................... -40 c to +85 c storage temperature range ............................ -65 c to +160 c lead temperature (soldering, 10sec) ............................ +300 c i source = 25 a, tx only v i rq = 5.5v i sink = 4ma dout only, cs = v cc shutdown mode active mode i source = 5ma v v cc = 3.3v v x1 = 0v and 5.5v conditions v cc - 0.5 v oh output high voltage pf 5 c out output capacitance a 1 i lk output leakage v 0.4 v ol output low voltage pf 5 c out output capacitance a 1 i lk output leakage dout, tx, rts : i sink = 4ma tx, rts : i sink = 25ma v pf 5 c in input capacitance v 0.3 x v cc v il input low voltage v 0.7 x v cc v ih input high voltage 0.4 v ol output low voltage 0.9 v x1 = 0v and 5.5v v v cc / 2 0.2 x v cc v il input low voltage v 0.7 x v cc v cc / 2 v ih input high voltage v 0.05 x v cc v hyst input hysteresis a 1 i il input leakage pf 5 c in input capacitance units min typ max symbol parameter 2 i in input current a 25 v cc - 0.5 ma 0.27 1 i cc v cc supply current in normal mode shdn bit = 1 or shdn = 0, logic inputs are at 0v or v cc a 10 i cc v cc supply current in shutdown with 1.8432mhz crystal; all other logic inputs are at 0v or v cc v cc = 5v v cc = 3.3v 0.15 0.4 v 2.7 5.5 v cc supply voltage logic inputs (din, sclk, cs , shdn , cts , rx) oscillator input (x1) outputs (dout, tx, rts ) irq output (open drain) power requirements
MAX3100 spi/micr owir e-compatible uar t in qsop-16 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +2.7v to +5.5v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) c load = 100pf c load = 100pf, r c s = 10k w c load = 100pf conditions ns 100 t cl sclk low time ns 100 t ch sclk high time ns 238 t cp sclk period ns 0 t dh din to sclk hold time ns 100 t ds din to sclk setup time ns 100 t do sclk fall to dout valid ns 0 t csh cs to sclk hold time ns 100 t css cs to sclk setup time ns 100 t tr cs high to dout tri-state ns 100 t dv cs low to dout valid units min typ max symbol parameter tx, rts , dout: c load = 100pf (note 1) ns 10 t r output rise time ns 200 t csw cs high pulse width ns 100 t cs0 sclk rising edge to cs falling (note 1) ns 200 t cs1 cs rising edge to sclk rising cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 1. detailed serial-interface timing tx, rts , dout, irq : c load = 100pf ns 10 t f output fall time ac timing (figure 1) note 1: t cs0 and t cs1 specify the minimum separation between sclk rising edges used to write to other devices on the spi bus and the cs used to select the MAX3100. a separation greater than t cs0 and t cs1 ensures that the sclk edge is ignored.
MAX3100 spi/micr owir e-compatible uar t in qsop-16 4 _______________________________________________________________________________________ __________________________________________ t ypical operating characteristics (t a = +25 c, unless otherwise noted.) 1000 900 0 -40 -20 40 60 100 supply current vs. temperature 200 100 800 700 MAX3100-01 temperature (?) supply current ( m a) 0 20 80 600 500 400 300 v cc = 3.3v v cc = 5v 1.8432mhz crystal transmitting at 115.2 kbps 10 9 0 -40 -20 40 60 100 shutdown current vs. temperature 2 1 8 7 MAX3100-02 temperature (?) shutdown current ( m a) 0 20 80 6 5 4 3 v cc = 5v v cc = 3.3v 1.8432mhz crystal 700 600 0 0 1 3 4 5 supply current vs. external clock frequency 100 500 MAX3100-03 external clock frequency (mhz) supply current ( m a) 2 400 300 200 v cc = 5v v cc = 3.3v 70 60 0 0 0.2 0.1 0.6 0.7 0.8 1.0 tx, rts, dout output current vs. output low voltage (v cc = 3.3v) 10 50 MAX3100-04 voltage (v) output sink current (ma) 0.3 0.5 0.4 0.9 40 30 20 rts tx dout 400 50 100 10k 1000 100k 1m supply current vs. baud rate 150 100 MAX3100-03a baud rate (bps) supply current ( m a) 200 250 350 300 5v transmitting 1.8432 mhz crystal 3v transmitting 5v standby 3v standby 90 80 0 0 0.2 0.1 0.6 0.7 0.8 1.0 tx, rts, dout output current vs. output low voltage (v cc = 5v) 10 70 MAX3100-05 voltage (v) output sink current (ma) 0.3 0.5 0.4 0.9 60 50 40 30 20 rts tx dout
MAX3100 spi/micr owir e-compatible uar t in qsop-16 _______________________________________________________________________________________ 5 ______________________________________________________________ pin description crystal connection. x1 also serves as an external clock input. see crystal-oscillator operation?1, x2 connection section. 9 10 general-purpose active-low input. read via the cts register bit; often used for rs-232 clear- to-send input (table 1). 10 11 general-purpose active-low output. controlled by the rts register bit. often used for rs-232 request-to-send output or rs-485 driver enable. 11 13 asynchronous serial-data (receiver) input. the serial information received from the modem or rs-232/rs-485 receiver. a transition on rx while in shutdown generates an interrupt (table 5). 12 14 asynchronous serial-data (transmitter) output 13 15 active-low interrupt output. open-drain interrupt output to microprocessor. 5 6 hardware-shutdown input. when shut down ( shdn = 0), the oscillator turns off immediately without waiting for the current transmission to end, reducing supply current to just leakage currents. 6 7 ground 7 8 crystal connection. leave x2 unconnected for external clock. see crystal-oscillator operation?1, x2 connection section. 8 9 active-low chip-select input. dout goes high impedance when cs is high. irq , tx, and rts are always active. schmitt-trigger input. 4 4 spi/microwire serial-clock input. schmitt-trigger input. 3 3 spi/microwire serial-data output. high impedance when cs is high. 2 2 spi/microwire serial-data input. schmitt-trigger input. 1 1 x1 cts rts rx tx irq shdn gnd x2 cs sclk dout din positive supply pin (2.7v to 5.5v) 14 16 no connection. not internally connected. 5, 12 v cc n.c. pin qsop function dip name _______________ detailed description the MAX3100 universal asynchronous receiver trans - mitter (uart) interfaces the spi/microwire-compatible, synchronous serial data from a microprocessor ( p) to asynchronous, serial-data communication ports (rs- 232, rs-485, irda). figure 2 shows the MAX3100 func - tional diagram. the MAX3100 combines a simple uart and a baud-rate generator with an spi interface and an interrupt genera - tor. configure the uart by writing a 16-bit word to a write-configuration register, which contains the baud rate, data-word length, parity enable, and enable of the 8-word receive first-in/first-out (fifo). the write configuration selects between normal uart timing and irda timing, controls shutdown, and contains 4 interrupt mask bits. transmit data by writing a 16-bit word to a write-data register, where the last 7 or 8 bits are actual data to be transmitted. also included is the state of the transmitted parity bit (if enabled). this register controls the state of the rts output pin. received words generate an inter - rupt if the receive-bit interrupt is enabled. read data from a 16-bit register that holds the oldest data from the receive fifo, the received parity data, and the logic level at the cts input pin. this register also contains a bit that is the framing error in normal operation and a receive-activity indicator in shutdown. the baud-rate generator determines the rate at which the transmitter and receiver operate. bits b0 to b3 in the write-configuration register determine the baud-rate divi - sor (brd), which divides down the x1 oscillator frequen - cy. the baud clock is 16 times the data rate (baud rate). the transmitter section accepts spi/microwire data, for - mats it, and transmits it in asynchronous serial format from the tx output. data is loaded into the transmit- buffer register from the spi/microwire interface. the MAX3100 adds start and stop bits to the data and clocks the data out at the selected baud rate (table 7).
MAX3100 spi/micr owir e-compatible uar t in qsop-16 6 _______________________________________________________________________________________ x1 x2 dout baud-rate generator spi interface baud-rate generator din sclk cs b0 pt tx-shift register start/stop- bit detect d0t?7t rx-shift register d0r?7r shdn fe ra xtal b1 b2 b3 rx tx 9 pt tx-buffer register 9 pr ra/fe (masks) pr r t rx-buffer register pr pr rx-buffer register 9 9 i / o cts rts irq interrupt logic transmit-done (tm) data-received (rm) parity (pm) framing error (ram)/ receive activity (sources) activity detect figure 2. functional diagram
MAX3100 spi/micr owir e-compatible uar t in qsop-16 _______________________________________________________________________________________ 7 the receiver section receives data in serial form. the MAX3100 detects a start bit on a high-to-low rx transi - tion (figure 3). an internal clock samples data at 16 times the data rate. the start bit can occur as much as one clock cycle before it is detected, as indicated by the shaded portion. the state of the start bit is defined as the majority of the 7th, 8th, and 9th sample of the internal 16x baud clock. subsequent bits are also majority sampled. receive data is stored in an 8-word fifo. the fifo is cleared if it overflows. the on-board oscillator can use a 1.8432mhz or 3.6864mhz crystal, or it can be driven at x1 with a 45% to 55% duty-cycle square wave. spi interface the bit streams for din and dout consist of 16 bits, with bits assigned as shown in the MAX3100 operations section. dout transitions on sclk? falling edge, and din is latched on sclk? rising edge (figure 4). most operations, such as the clearing of internal registers, are executed only on cs ? rising edge. the din stream is monitored for its first two bits to tell the uart the type of data transfer being executed (write config, read config, write data, read data). only 16-bit words are expected. if cs goes high in the middle of a transmission (any time before the 16th bit), the sequence is aborted (i.e., data does not get written to individual registers). every time cs goes low, a new 16-bit stream is expected. an example of a write con - figuration is shown in figure 4. 1 rx baud block 2 3 4 5 6 7 8 9 one baud period 10 11 majority center sampler 12 13 14 15 16 a figure 3. start-bit timing 1 cs sclk din dout 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data updated 1 1 fen shdn tm rm pm ram ir st pe l b3 b2 b1 b0 r t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 4. spi interface (write configuration)
MAX3100 spi/micr owir e-compatible uar t in qsop-16 8 _______________________________________________________________________________________ MAX3100 operations write operations table 1 shows write-configuration data. a 16-bit spi/microwire write configuration clears the receive fifo and the r, t, ra/fe, d0r?7r, d0t?7t, pr, and pt registers. rts and cts remain unchanged. the new configuration is valid on cs ? rising edge if the transmit buffer is empty (t = 1) and transmission is over. if the latest transmission has not been completed, the regis - ters are updated when the transmission is over (t = 0). the write-configuration bits ( fen , shdni, ir, st, pe, l, b3?0) take effect after the current transmission is over. the mask bits ( tm , rm , pm , ram ) take effect immediately after the 16th clock? rising edge at sclk. read operations table 2 shows read-configuration data. this register reads back the last configuration written to the MAX3100. the device enters test mode if bit 0 = 1. in this mode, if cs = 0, the rts pin acts as the 16x clock generator? output. this may be useful for direct baud- rate generation (in this mode, tx and rx are in digital loopback). normally, the write-data register loads the tx-buffer register. to change the rts pin? state without writing data, set the te bit. setting the te bit high inhibits the write command (table 3). reading data clears the r bit and interrupt irq (table 4) . register functions table 5 shows read/write operation and power-on reset state (por), and describes each bit used in program - ming the MAX3100. figure 5 shows parity and word- length control. 14 0 t 6 d6t d6r 7 d7t d7r 15 2 din 1 d2t dout r d2r bit 3 d3t d3r 0 d0t d0r 1 d1t d1r 4 d4t d4r 5 d5t d5r 10 te ra/fe 11 0 0 8 pt pr 9 rts cts 12 0 0 13 0 0 14 0 t 6 0 d6r 7 0 d7r 15 2 din 0 0 dout r d2r bit 3 0 d3r 0 0 d0r 1 0 d1r 4 0 d4r 5 0 d5r 10 0 ra/fe 11 0 0 8 0 pr 9 0 cts 12 0 0 13 0 0 table 3. write data (d15, d14 = 1, 0) table 4. read data (d15, d14 = 0, 0) 14 1 t 6 0 st 7 0 ir 15 2 din 0 0 dout r b2 bit 3 0 b3 0 test b0 1 0 b1 4 0 l 5 0 pe 10 0 rm 11 0 tm 8 0 ram 9 0 pm 12 0 shdno 13 0 fen table 2. read configuration (d15, d14 = 0, 1) 6 st 0 7 ir 0 2 b2 0 3 b3 0 0 b0 0 1 b1 0 4 l 0 5 pe 0 10 rm 0 11 tm 0 8 ram 0 9 pm 0 12 shdni 0 13 fen 0 15 14 1 t din 1 dout r bit table 1. write configuration (d15, d14 = 1, 1)
MAX3100 spi/micr owir e-compatible uar t in qsop-16 _______________________________________________________________________________________ 9 por state description 0000 0000 x pr r receive-parity bit. this bit is the extra bit received if pe = 1. therefore, pe = 1 results in 9-bit transmissions (l = 0). if pe = 0, then pr is set to 0. pr is stored in the fifo with the receive data (see the nine-bit networks section). 0 0 ir r reads the value of the ir bit. l read/ write w b0?3 w baud-rate divisor select bits. sets the baud clock? value (table 6). b0?3 r baud-rate divisor select bits. reads the 4-bit baud clock value assigned to these registers. bit name bit for setting the word length of the transmitted or received data. l = 0 results in 8-bit words (9-bit words if pe = 1), see figure 5. l = 1 results in 7-bit words (8-bit words if pe = 1). 0 x l r reads the value of the l bit. pt w transmit-parity bit. this bit is treated as an extra bit that will be transmitted if pe = 1. to be useful in 9-bit networks, the MAX3100 does not calculate parity. if pe = 0, then this bit (pt) is ignored in transmit mode (see the nine-bit networks section). 00000000 0 d0r?7r r eight data bits read from the receive fifo or the receive register. these will be all 0s when the receive fifo or the receive registers are empty. when l = 1, d7r is always 0. fen w fifo enable. enables the receive fifo when fen = 0. when fen = 1, fifo is disabled. 0 0 fen r fifo-enable readback. fen ? state is read. ir w enables the irda timing mode when ir = 1. no change x cts r clear-to-send-input. records the state of the cts pin (cts bit = 0 implies cts pin = logic high). d0t?7t w transmit-buffer register. eight data bits written into the transmit-buffer register. d7t is ignored when l = 1. table 5. bit descriptions 0 pe w parity-enable bit. appends the pt bit to the transmitted data when pe = 1, and sends the pt bit as written. no parity bit is transmitted when pe = 0. with pe = 1, an extra bit is expected to be received. this data is put into the pr register. pr = 0 when pe = 0. the MAX3100 does not calculate parity. 0 pe r reads the value of the parity-enable bit. 0 pm w mask for pr bit. irq is asserted if pm = 1 and pr = 1 (table 6). 0 pm r reads the value of the pm bit (table 6). 0 r r receive bit or fifo not empty flag. r = 1 means new data is available to be read from the receive register or fifo. 0 rm w mask for r bit. irq is asserted if rm = 1 and r = 1 (table 6). 0 rm r reads the value of the rm bit (table 6). 0 ram w mask for ra/fe bit. irq is asserted if ram = 1 and ra/fe = 1 (table 6). 0 ram r reads the value of the ram bit (table 6). 0 rts w request-to-send bit. controls the state of the rts output. this bit is reset on power-up (rts bit = 0 sets the rts pin = logic high).
MAX3100 spi/micr owir e-compatible uar t in qsop-16 10 ______________________________________________________________________________________ table 5. bit descriptions (continued) por state description read/ write bit name 0 shdni w software-shutdown bit. enter software shutdown with a write configuration where shdni = 1. software shutdown takes effect after cs goes high, and causes the oscillator to stop as soon as the transmitter becomes idle. software shutdown also clears r, t, ra/fe, d0r?7r, d0t?7t, pr, pt, and all data in the receive fifo. rts and cts can be read and updated while in shutdown. exit software shutdown with a write configuration where shdni = 0. the oscillator restarts typically within 50ms of cs going high. rts and cts are unaffected. refer to the pin description for hardware shutdown ( shdn input). 0 shdno r shutdown read-back bit. the read-configuration register outputs shdno = 1 when the uart is in shutdown. note that this bit is not sent until the current byte in the transmitter is sent (t = 1). this tells the processor when it may shut down the rs-232 driver. this bit is also set imme - diately when the device is shut down through the shdn pin. 0 ra/fe r receiver-activity/framing-error bit. in shutdown mode, this is the ra bit. in normal operation, this is the fe bit. in shutdown mode, a transition on rx sets ra = 1. in normal mode, a fram - ing error sets fe = 1. a framing error occurs if a zero is received when the first stop bit is expected. fe is set when a framing error occurs, and cleared upon receipt of the next proper - ly framed character independent of the fifo being enabled. when the device wakes up, it is likely that a framing error will occur. this error can be cleared with a write configuration. the fe bit is not cleared on a read data operation. when an fe is encountered, the uart resets itself to the state where it is looking for a start bit. 0 st w transmit-stop bit. one stop bit will be transmitted when st = 0. two stop bits will be transmit - ted when st = 1. the receiver only requires one stop bit. 0 st r reads the value of the st bit. 0 tm w mask for t bit. irq is asserted if tm = 1 and t = 1 (table 6). 0 tm r reads the value of the tm bit (table 6). 1 t r transmit-buffer-empty flag. t = 1 means that the transmit buffer is empty and ready to accept another data word. 0 te w transmit-enable bit. if te = 1, then only the rts pin will be updated on cs ? rising edge. the contents of rts , pt, and d0t?7t transmit on cs ? rising edge when te = 0. idle second stop bit is omitted if st = 0. pe = 1, l = 1 time d0 start d1 d2 d3 d4 d5 d6 pt stop stop idle idle pe = 1, l = 0 d0 start d1 d2 d3 d4 d5 d6 d7 pt stop stop idle idle pe = 0, l = 1 d0 start d1 d2 d3 d4 d5 d6 stop stop idle idle pe = 0, l = 0 d0 start d1 d2 d3 d4 d5 d6 d7 stop stop idle figure 5. parity and word-length control
MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 11 irq n rm mask tm mask pm mask transition on rx shutdown ram mask framing error shutdown ram mask r s q r new data available data read transmit buffer empty data read pe = 1 and received parity bit = 1 pe = 0 or received parity bit = 0 t pr ra fe r s q r s q figure 6. interrupt sources and masks functional diagram table 6. interrupt sources and masks?it descriptions meaning when set description received parity bit = 1 transition on rx when in shutdown; framing error when not in shutdown ra/fe ram this is the ra (rx-transition) bit in shutdown, and the fe (framing-error) bit in operating mode. ra is set if there has been a transition on rx since entering shutdown. ra is cleared when the MAX3100 exits shutdown. irq is asserted when ra is set and ram = 1. fe is determined solely by the currently received data, and is not stored in fifo. the fe bit is set if a zero is received when the first stop bit is expected. fe is cleared upon receipt of the next properly framed character. irq is asserted when fe is set and ram = 1. mask bit pr pm the pr bit reflects the value in the word currently in the receive-buffer register (oldest data available). the pr bit is set when parity is enabled (pe = 1) and the received parity bit is 1. the pr bit is cleared either when parity is not enabled (pe = 0), or when parity is enabled and the received bit is 0. an interrupt is issued based on the oldest pr value in the receiver fifo. the oldest pr value is the next value that will be read by a read data operation. bit name data available r rm the r bit is set when new data is available to be read from the receive register/ fifo. fifo is cleared when all data has been read. an interrupt is asserted as long as r = 1 and rm = 1. transmit buffer is empty t tm the t bit is set when the transmit buffer is ready to accept data. irq is asserted low if tm = 1 and the transmit buffer becomes empty. this source is cleared on cs ? rising edge during a read data operation. although the interrupt is cleared, t may be polled to determine transmit-buffer status. interrupt sources and masks a read data operation clears the interrupt irq . table 6 gives the details for each interrupt source. figure 6 shows the functional diagram for the interrupt sources and mask blocks.
clock-oscillator baud rates bits b0?3 of the write-configuration register determine the baud rate. table 7 shows baud-rate divisors for given input codes, as well as the given baud rate for 1.8432mhz and 3.6864mhz crystals. note that the baud rate = crystal frequency / 16x division ratio. shutdown mode in shutdown, the oscillator turns off to reduce power dissipation (i cc < 10 a). the MAX3100 enters shut - down in one of two ways: by a software command (shdni bit = 1) or by a hardware command ( shdn = logic low). the hardware shutdown is effective immedi - ately and will immediately terminate any transmission in progress. the software shutdown, requested by setting shdni bit = 1, is entered upon completing the trans - mission of the data in both the transmit register and the transmit-buffer register. the shdno bit is set when the MAX3100 enters shutdown (either hardware or soft - ware). the microcontroller ( c) can monitor the shdno bit to determine when all data has been transmitted, and shut down any external circuitry (such as rs-232 transceivers) at that time. shutdown clears the receive fifo, r, a, ra/fe, d0r?7r, pr, and pt registers and sets the t bit high. configuration bits ( rm , tm , pm , ram , ir, st, pe, l, b0-3, and rts) can be modified when shdno = 1 and cts can also be read. even though ra is reset upon entering shutdown, it will go high when any transitions are detected on the rx pin. this allows the uart to monitor activity on the receiver when in shutdown. the command to power up (shdni = 0) turns on the oscillator when cs goes high if shdn pin = logic high, with a start-up time of about 25ms. this is done through a write configuration, which clears all registers but rts and cts . since the crystal oscillator typically requires 25ms to start, the first received characters will be gar - bled, and a framing error may occur. __________ applications infor mation driving opto-couplers figure 7 shows the MAX3100 in an isolated serial inter - face. the MAX3100 schmitt-trigger inputs are driven directly by opto-coupler outputs. isolated power is pro - vided by the max845 transformer driver and linear reg - ulator shown. a significant feature of this application is that the opto-coupler? skew does not affect the asyn - chronous serial output? timing. only the set-up and hold times of the spi interface need to be met. figure 8 shows a bidirectional opto-isolated interface using only two opto-isolators. over 81% power savings is realized using irda mode due to its 3/16-wide baud periods. crystal-oscillator operation x1, x2 connection the MAX3100 includes a crystal oscillator for baud-rate generation. for standard baud rates, use a 1.8432mhz or 3.6864mhz crystal. the 1.8432mhz crystal results in lower operating current; however, the 3.6864mhz crys - tal may be more readily available in surface mount. ceramic resonators are low-cost alternatives to crystals and operate similarly, though the ??and accuracy are lower. some ceramic resonators are available with inte - gral load capacitors, which can further reduce cost. the tradeoff between crystals and ceramic resonators is in initial frequency accuracy and temperature drift. the total error in the baud-rate generator should be kept below 1% for reliable operation with other sys - tems. this is accomplished easily with a crystal, and in most cases can be achieved with ceramic resonators. table 8 lists the different types of crystals and res - onators and their suppliers. MAX3100 spi/micr owir e-compatible uar t in qsop-16 12 ______________________________________________________________________________________ table 7. baud-rate selection table* *standard baud rates shown in bold **default baud rate 115.2k 230.4k** baud rate (f osc = 3.6864mhz) baud b3 b2 b1 b0 2 0 0 0 1 1 0 0 0 0** division ratio 57.6k 115.2k** baud rate (f osc = 1.8432mhz) 28.8k 57.6k 8 0 0 1 1 4 0 0 1 0 14.4k 28.8k 7200 14.4k 1800 3600 128 0 1 1 1 64 0 1 1 0 900 1800 32 0 1 0 1 16 0 1 0 0 3600 7200 38.4k 76.8k 9600 19.2k 24 1 0 1 1 12 1 0 1 0 4800 9600 2400 4800 600 1200 384 1 1 1 1 192 1 1 1 0 300 600 96 1 1 0 1 48 1 1 0 0 1200 2400 6 1 0 0 1 3 1 0 0 0 19.2k 38.4k
MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 13 MAX3100 max3222 cs iso 5v sclk iso +5v tx din 2k 6n136 6n136 6n136 6n136 2k 2k 2k dout cs sclk din dout iso +5v v cc v cc +5v mbr0520 halo tgm-010p3 v cc v cc 470 w rx cts rts max253 max667 470 w 470 w 470 w linear regulator transformer driver figure 7. driving optocouplers
MAX3100 spi/micr owir e-compatible uar t in qsop-16 14 ______________________________________________________________________________________ MAX3100 cs sclk din dout tx rx +5v iso +5v +5v v cc gnd MAX3100 cs sclk din dout rx 470 w 470 w 2k 2k tx v cc gnd figure 8. bidirectional opto-isolated interface table 8. component and supplier list this oscillator supports parallel-resonant mode crystals and ceramic resonators, or can be driven from an external clock source. internally, the oscillator consists of an inverting amplifier with its input, x1, tied to its out - put, x2, by a bias network that self-biases the inverter at approximately v cc / 2. the external feedback circuit, usually a crystal, from x2 to x1 provides 180 of phase shift, causing the circuit to oscillate. as shown in the standard application circuit, the crystal or resonator is connected between x1 and x2, with the load capaci - tance for the crystal being the series combination of c1 and c2. for example, a 1.8432mhz crystal with a spec - ified load capacitance of 11pf would use capacitors of 22pf on either side of the crystal to ground. series-res - onant mode crystals have a slight frequency error, typi - cally oscillating 0.03% higher than specified series- resonant frequency, when operated in parallel mode. it is very important to keep crystal, resonator, and load-capacitor leads and traces as short and direct as possible. the x1 and x2 trace lengths and ground tracks should be tight, with no other intervening traces. this helps minimize parasitic capacitance and noise pickup in the oscillator, and reduces emi. minimize capacitive loading on x2 to minimize supply current. murata north america ecs international, inc. supplier csa1.84mg ecs-18-13-1 part number (800) 831-9172 (913) 782-7787 phone number description 1.8432 through-hole resonator 1.8432 through-hole crystal (hc-49/u) frequency (mhz) 47 25 typical c1, c2 (pf) ecs international, inc. ecs international, inc. ecs-36-20-5p ecs-36-18-4 (913) 782-7787 (913) 782-7787 3.6864 smt crystal 3.6864 through-hole crystal (hc-49/us) 39 33 avx/kyocera pbrc-3.68b (803) 448-9411 3.6864 smt resonator none (integral)
the MAX3100 x1 input can be driven directly by an external cmos clock source. the trip level is approxi - mately equal to v cc / 2. no connection should be made to x2 in this mode. if a ttl or non-cmos clock source is used, ac couple with a 10nf capacitor to x1. the peak-to-peak swing on the input should be at least 2v for reliable operation. 9-bit networks the MAX3100 supports a common multidrop communi - cation technique referred to as 9-bit mode. in this mode, the parity bit is set to indicate a message that contains a header with a destination address. the MAX3100 parity mask can be set to generate interrupts for this condition. operating a network in this mode reduces the process - ing overhead of all nodes by enabling the slave con - trollers to ignore most message traffic. this can relieve the remote processor to handle more useful tasks. i n 9-bit mode, the MAX3100 is set up with 8 bits plus parity. the parity bit in all normal messages is clear, but is set in an address-type message. the MAX3100 pari - ty-interrupt mask is enabled to generate an interrupt on high parity. when the master sends an address mes - sage with the parity bit set, all MAX3100 nodes issue an interrupt. all nodes then retrieve the received byte to compare to their assigned address. once addressed, the node continues to process each received byte. if the node was not addressed, it ignores all message traffic until a new address is sent out by the master. the parity/9th-bit interrupt is controlled only by the data in the receive register, and is not affected by data in the fifo, so the most effective use of the parity/9th-bit interrupt is with fifo disabled. with the fifo disabled, received nonaddress words can be ignored and not even read from the uart. sir irda mode the MAX3100? irda mode can be used to communicate with other irda sir-compatible devices, or to reduce power consumption in opto-isolated applications. in irda mode, a bit period is shortened to 3/16 of a baud period (1.6 s at 115,200 baud) (figure 9). a data zero is transmitted as a pulse of light (tx pin = logic low, rx pin = logic high). in receive mode, the rx signal? sampling is done halfway into the transmission of a high level. the sam - pling is done once, instead of three times, as in normal mode. the MAX3100 ignores pulses shorter than approximately 1/16 of the baud period. the irda device that is communicating with the MAX3100 must be set to transmit pulses at 3/16 of the baud period. for compati - bility with other irda devices, set the format to 8-bit data, one stop, no parity. irda module the MAX3100 was optimized for direct optocoupler drive, whereas irda modules contain inverting buffers. invert the rx and tx outputs as shown in figure 10. 8051 example: irda to rs-232 converter figure 10 shows the MAX3100 with an 8051 c. this circuit receives irda data and outputs standard rs-232 data. although the 8051 contains an internal uart, it does not support irda or high-speed communications. the MAX3100 can easily interface to the 8051 to sup - port these high-performance communications modes. the 8051 does not have an spi interface, so communi - cation with the MAX3100 is accomplished with port pins and a short software routine (figure 12a). the software routine polls the irq output to see if data is available from the MAX3100 uart. it then shifts the data out, using the 8051 port pins, and transmits it out the rs-232 side through the max3221 driver. the 8051 simultaneously monitors its internal uart for incoming communications from the rs-232 side, and transmits this data out the irda side through the MAX3100. the low-level routine (utlk) is the core routine that sends and receives data over the port pins to simulate an spi port on the 8051. this technique is useful for any 8051- based MAX3100 port-pin-interfaced application. MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 15 start stop start stop normal rx uart frame data bits 0 1 1 1 1 1 0 0 0 0 normal uart tx 1 1 1 1 1 0 0 0 0 irda rx irda tx figure 9. irda timing
MAX3100 spi/micr owir e-compatible uar t in qsop-16 16 ______________________________________________________________________________________ MAX3100 3100 irq rx tx rx tx rxd txd 22pf 22pf 330 w ir led +5v 1/6 hc00 1/6 hc00 direct opto-coupler drive or ir module drive ir module 8051 max3221 100 w 0.1 m f +5v 1.8432mhz 10k figure 10. bidirectional rs-232 irda using an 8051 interface to pic processor (?uick brown fox?generator) figure 11 illustrates the use of the MAX3100 with the pic . this circuit is a ?uick brown fox?generator that repeatedly transmits ?he quick brown fox jumps over the lazy dog?(covering the entire alphabet) over an rs-232 link with adjustable baud rate, word length, and delay. although a software-based uart could be implemented on the pic, features like accu - rate variable baud rates, high baud rates, and simple protocol selection would be difficult to implement reli - ably. the 16c54 in the example is the most basic of the pics. thus, it is possible to implement the example on any member of the pic family. the software routine (figure 12) begins by reading the dip switch on port rb. the switch data includes 4 bits for the baud rate, 1 bit for number of stop bits, 1 bit for a word length of 7 or 8 bits, and 1 bit for delay between messages. the pic reads the switch only at initializa - tion (reset), and programs the parameters into the MAX3100. it then begins sending the message repeat - edly. if the delay bit is set, it inserts a 1sec delay between transmissions. as in the 8051 example, the main routine is called utlk, and can be used in any pic-based, port-pin-interfaced application. pic is a registered trademark of microchip corporation.
MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 17 pic16c54 v cc x1 x2 rb7 rb6 rb5 tx 22pf 22pf rb4 rb3 rb2 rb1 rb0 go y/n 1 m s delay 1/2 stop bits tx 7/8 bits b3 ra0 ra1 ra2 ra3 dout din sclk cs b2 b1 b0 100k 100k 100k 100k 100k 100k 100k 100k 1. 8432mhz MAX3100 max3221 figure 11. quick brown fox generator
MAX3100 spi/micr owir e-compatible uar t in qsop-16 18 ______________________________________________________________________________________ table 10. synchronous data output format (dout pin to microprocessor, spi miso) fen 0 shdno 0 pm 0 ram 0 tm 0 rm 0 pe 0 l 0 b1 0 b0 0 b3 0 b2 r read config 0 r write config ir (irda) 0 st 0 0 0 0 0 cts t t cts pr pr 0 0 ra/ fe ra/ fe d5r d5r d4r d4r d1r d1r d0r d0r d3r d3r d2r r read data d2r r write data d7r d7r d6r d6r t t __________ MAX3100 synchr onous-to-asynchr onous spi uar t at a glance table 9. synchronous data input format (din pin from microprocessor, spi mosi) 0 0 d6t 0 d7t 0 write data 1 d2t read data 0 0 d3t 0 d0t 0 d1t 0 d4t 0 d5t 0 te 0 0 0 pt 0 rts 0 0 0 0 0 1 1 st 0 ir (irda) 0 write config 1 b2 read config 0 0 b3 0 bit number b0 test b1 0 l 0 pe 0 rm 0 tm 0 ram 0 pm 0 shdni 0 fen 0 14 6 7 15 2 oper- ation 3 0 1 4 5 10 11 8 9 12 13 bit number 13 12 9 8 11 10 5 4 1 0 3 oper- ation 2 15 7 6 14
table 11. bit definitions* table 13. 1.8432mhz baud rates table 12. field definitions * default setting is clear MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 19 baud 115.2k b3...b0 56k 0 0 0 1 2 0 0 0 0 1 28k 0 0 1 0 4 14k brd 0 0 1 1 8 baud 38.4k b3...b0 19.2k 1 0 0 1 6 1 0 0 0 3 9600 1 0 1 0 12 4800 brd 1 0 1 1 24 2400 1200 1 1 0 1 96 1 1 0 0 48 600 1 1 1 0 192 300 1 1 1 1 384 7200 3600 0 1 0 1 32 0 1 0 0 16 1800 0 1 1 0 64 900 0 1 1 1 128 meaning register field name baud-rate divisor transmit data write data d7t?0t config b3?0 received parity bit read data pr received data read data d7r?0r parity disabled parity enabled config pe enable fifo buffer disable fifo buffer bit set (1) bit clear (0) operate shutdown config shdni disable transmit- done interrupt enable transmit- done interrupt disable data- received interrupt enable data- received inter - rupt config rm config tm disable parity interrupt enable parity interrupt disable framing- error interrupt enable framing- error interrupt config ram standard timing enable irda timing mode one stop bit two stop bits config st config ir config pm config register fen bit name bit set (1) bit clear (0) word length = 8 bits word length = 7 bits config l enable normal operation inhibit tx output register drive rts out - put pin high drive rts output pin low write data rts write data te transmit parity = 0 transmit parity = 1 write data pt normal data overrun or framing error cts input pin is high cts input pin is low read data cts data buffer is empty data has been received uart is busy transmitting transmit buffer is empty all t all r bit name read data ra/fe
MAX3100 spi/micr owir e-compatible uar t in qsop-16 20 ______________________________________________________________________________________ figure 12a. 8051 irda/rs-232 code
figure 12b. MAX3100 using pic c MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 21
MAX3100 spi/micr owir e-compatible uar t in qsop-16 22 ______________________________________________________________________________________ figure 12b. MAX3100 using pic c (continued)
___________________________________________________ t ypical operating cir cuit rx cts rts tx din dout spi/microwire rs-232 i/o sclk cs c2 c1 MAX3100 irq max3223 m c MAX3100 spi/micr owir e-compatible uar t in qsop-16 ______________________________________________________________________________________ 23
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. MAX3100 spi/micr owir e-compatible uar t in qsop-16 ___________________ chip infor mation transistor count: 6848 substrate connected to gnd ________________________________________________________ package infor mation qsop.eps

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